The continual demand for enhanced integrated circuit performance has resulted in, among other things, a dramatic reduction of semiconductor device geometries, and continual efforts to optimize the performance of every substructure within any semiconductor device. A number of improvements and innovations in fabrication processes, material composition, and layout of the active circuit levels of a semiconductor device have resulted in very high-density circuit designs. Increasingly dense circuit design has not only improved a number of performance characteristics, it has also increased the importance of, and attention to, semiconductor material properties and behaviors.
The increased packing density of the integrated circuit generates numerous challenges to the semiconductor manufacturing process. Nearly every device must be smaller without degrading operational performance of the integrated circuitry. High packing density, low heat generation, and low power consumption, with good reliability must be maintained without any functional degradation. Increased packing density of integrated circuits is usually accompanied by smaller feature size and, correspondingly, smaller device geometries.
As semiconductor feature sizes and geometries are reduced, certain device structures become more sensitive to physical properties and behaviors of other nearby device structures. Minor changes in placement or configuration of a device structure can have a significant impact on the lifetime performance or reliability of an integrated circuit. Balancing competing sensitivities and characteristics of different structures within a circuit can be further complicated by technology-imposed design or layout limitations. A number of high-performance device fabrication technologies must impose certain design constraints (e.g., maximum interconnect width, maximum oxide thickness, minimum gate length) in order to provide required performance levels (e.g., low voltage operation).
Consider, for example, certain issues that arise during the production and operation of low voltage CMOS transistor devices. The use of low supply voltage (e.g., 1.2V, 1.8V) CMOS components within certain applications—especially applications where such components are interfaced to higher voltage (e.g., 1.8V, 3.0V) devices—can result in disproportionately high stresses on critical CMOS features and structures. One CMOS device feature of particular concern is gate oxide. The electrical integrity and stability of gate oxide structure is critical to overall transistor performance and reliability. However, CMOS transistor gate oxides can be vulnerable to structural and parametric breakdown caused by high electric fields generated from within a transistor—especially relatively shallow gate oxides that are common in low voltage technologies.
Such internally generated electric fields frequently occur where a low supply voltage CMOS transistor is utilized in an application having high transistor terminal bias voltages (i.e., high bias on either the transistor's drain or supply). Unfortunately, such applications are commonplace for CMOS transistors. In many cases, it is desirable to design a system incorporating as many low supply voltage devices as possible, even where those low supply voltage devices must be used in conjunction with relatively high signal voltage devices.
Moreover, the generation of, and damage caused by, internal electric fields can be intensified by device features and spatial relationships necessitated by the device's fabrication technology. For example, a number of small geometry CMOS transistor technologies utilize a shallow trench isolation (STI) feature within device silicon to separate gate structure from drain structure. Commonly, however, the configuration and placement of STI features conduct, or promote the conduction of, electric fields from the drain region orthogonally into the gate oxide.
As most, if not all, of an orthogonal electric field penetrates a gate oxide, that oxide rapidly begins to break down. As gate oxide breakdown continues, device parametric performance skews drastically until the device fails completely. This obviously causes a number of circuit and system performance and reliability problems. A manufacturer's ability to address such phenomena, and problems resulting therefrom, is often limited or precluded by process technology design constraints. In a low voltage technology, for example, increasing gate oxide thickness to withstand electric field degradation is often not possible or commercially feasible. Altering process flows or design rules, to overcome such technology-imposed constraints on a general or case-by-case basis, is inefficient and cost-prohibitive.
As a result, there is a need for a system that effectively limits semiconductor structure degradation caused by internally generated electric fields—improving overall circuit and system performance and reliability in an easy, efficient and cost-effective manner.